Verilog Programs Have Stream Semantics (Verilog basics 2)
When discussing programming languages, there are often two axes that we care about: syntax and semantics. In my first post about Verilog, I discussed the interesting points of Verilog's syntax. This post will discuss Verilog semantics. Specifically, whereas the first post covered the basics of structural Verilog, this post will introduce the basics of behavioral Verilog.